The CMOS image sensor (hereinafter to be referred to as a CMOS sensor) prepared using a CMOS logic process is also known as an APS (active pixel sensor) with an amplifier contained in the light-receiving portion of the chip.
In this system, the charge generated by light is subject to current amplification and then output from the light-receiving portion, and this enhances the image quality.
For example, the CMOS image sensor comprising of 3-5 transistors that form an amplifier for each pixel (typically, a CMOS sensor comprises four transistors) is in wide application.
In the 4-transistor CMOS sensor, however, the numerical aperture is only about 20% due to the area occupied by the amplifier in the light-receiving portion, and it is hard to further increase the numerical aperture. Also, it is hard to reduce the size of the pixels. This is undesirable. Consequently, improvement of the sensor characteristics depends significantly on forming finer elements in the CMOS process.
Also, the structure of the sensor makes impossible to realize complete evacuation of the signal charge, and the noise accompanying the reset operation, known as kTC noise is contained in the signal component. This is a major problem that hampers practical application of the sensor.
On the other hand, a novel type of CMOS sensor that includes a charge-detecting portion allowing complete evacuation of the signal charge in reset has been under development as a CMOS sensor with a light-receiving portion that allows complete evacuation. This type of CMOS sensor can realize a high image quality with zero kTC noise. Consequently, it has a latent ability and allows high-speed driving. This is an advantage.
There are several reports on the CMOS sensors with said light-receiving portion that allows complete evacuation.
As described in one report, T. Miida, et al.: “1.5M Pixel Imager with Localized Hole Modulation Method,” ISSCC Digest of Technical Papers, USA, Vol. 55, February 2002, a type of CMOS sensor known as a MOS gate threshold modulation-type, and having a structure wherein charge-detecting current flows in the in-plane direction of the substrate, has been developed that has a numerical aperture of about 30%.
In use, however, the gate for charge detection and the gate for pixel selection are shared in the CMOS sensor of the MOS gate threshold modulation-type. Consequently, when an intense beam of light is incident, the source current of the unselected pixels flows out, forming a black smear. Consequently, this scheme is problematic in its concept.
Also, a type of charge-detecting portion has been developed with a structure in which the charge-detecting current flows in the depth direction (hereinafter to be referred to as the vertical direction) of the silicon wafer by means of a vertical pnp transistor (junction transistor) Japanese Kokai Patent Application No. 2002-0054225. In the following, it will be referred to as a vertical pnp transistor type sensor.
The numerical aperture of the vertical pnp transistor type sensor is about 30%, and its charge-detecting current can be higher than that of the MOS gate threshold modulation-type CMOS sensor. Consequently, the Johnson noise can be reduced significantly.
Also, because the gate for pixel selection can be separated from the charge-detecting portion, this type of sensor is preferred over the MOS gate threshold modulation-type CMOS sensor with respect to the problem of black smear.
When the sensor of the vertical pnp transistor type is adopted as a CMOS sensor, however, contact is necessary in the source/drain region for flow of the charge-detecting current in the light-receiving portion. This is undesirable.
That is, although it is preferred that the charge-detecting portion be directly used as a light-receiving portion from the standpoint of effective use of area, the wiring for contact of the source/drain region nevertheless blocks light from the light-receiving portion, leading to a low numerical aperture. In addition, when the silicide process is adopted, there are problems pertaining to dark current, damages, etc., because a contact is present in the light-receiving portion, it is hard to adjust the doping concentration in the lower portion of the silicide, and it is difficult to ensure the characteristics of the vertical pnp transistor. This is a new problem.
On the other hand, when the light-receiving portion is arranged separately, there should be an area for the gate for transfer and for the charge-detecting portion. Consequently, the area of the light-receiving portion cannot be large, and the numerical aperture becomes smaller.
Also, each pixel should have a transistor for selecting the desired pixel. When conventional NMOS transistors are used, however, there should be an area for element separation, leading to further decrease in the numerical aperture.
As explained above, the conventional image sensors have a common disadvantage that the area of the light-receiving portion is insufficient. This indicates that there is insufficient margin for sensitivity and resolution as important characteristics of the image sensor. Although certain improvements may be realized by means of fine processing technology and OCL (on chip lens), it is impossible to adopt the fine processing technology of CMOS as is because the leakage current required in the conventional CMOS is different from that required for the image sensor. Also, when the area of the light-receiving portion is small, the sensitivity varies depending on the OCL focus position. Consequently, a special lens design should be performed for lenses with a large F-value.
A general object of this invention is to solve problems in the prior art by providing a type of solid-state image sensing device in which a structure that can realize zero kTC noise, it can suppress black smear and dark current, and it can increase the numerical aperture and eliminate the problem of insufficient area of the light-receiving portion.